REG0_STEP_TIME=64_CLOCKS, AUDIO_DIV_LSB=AUDIO_DIV_LSB_0, REG2_STEP_TIME=64_CLOCKS, REG1_STEP_TIME=64_CLOCKS, AUDIO_DIV_MSB=AUDIO_DIV_MSB_0, PLL3_disable=PLL3_disable_0, VIDEO_DIV=VIDEO_DIV_0
Miscellaneous Register 2
| REG0_BO_OFFSET | This field defines the brown out voltage offset for the CORE power domain 4 (REG0_BO_OFFSET_4): Brownout offset = 0.100V 7 (REG0_BO_OFFSET_7): Brownout offset = 0.175V |
| REG0_BO_STATUS | Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) 1 (REG0_BO_STATUS_1): Brownout, supply is below target minus brownout offset. |
| REG0_ENABLE_BO | Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) |
| REG0_OK | ARM supply Not related to CCM. See Power Management Unit (PMU) |
| PLL3_disable | When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode 0 (PLL3_disable_0): PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode 1 (PLL3_disable_1): PLL3 can be disabled when the SoC is not in any low power mode |
| REG1_BO_OFFSET | This field defines the brown out voltage offset for the xPU power domain 4 (REG1_BO_OFFSET_4): Brownout offset = 0.100V 7 (REG1_BO_OFFSET_7): Brownout offset = 0.175V |
| REG1_BO_STATUS | Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) 1 (REG1_BO_STATUS_1): Brownout, supply is below target minus brownout offset. |
| REG1_ENABLE_BO | Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) |
| REG1_OK | GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) |
| AUDIO_DIV_LSB | LSB of Post-divider for Audio PLL 0 (AUDIO_DIV_LSB_0): divide by 1 (Default) 1 (AUDIO_DIV_LSB_1): divide by 2 |
| REG2_BO_OFFSET | This field defines the brown out voltage offset for the xPU power domain 4 (REG2_BO_OFFSET_4): Brownout offset = 0.100V 7 (REG2_BO_OFFSET_7): Brownout offset = 0.175V |
| REG2_BO_STATUS | Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) |
| REG2_ENABLE_BO | Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) |
| REG2_OK | Signals that the voltage is above the brownout level for the SOC supply |
| AUDIO_DIV_MSB | MSB of Post-divider for Audio PLL 0 (AUDIO_DIV_MSB_0): divide by 1 (Default) 1 (AUDIO_DIV_MSB_1): divide by 2 |
| REG0_STEP_TIME | Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 0 (64_CLOCKS): 64 1 (128_CLOCKS): 128 2 (256_CLOCKS): 256 3 (512_CLOCKS): 512 |
| REG1_STEP_TIME | Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 0 (64_CLOCKS): 64 1 (128_CLOCKS): 128 2 (256_CLOCKS): 256 3 (512_CLOCKS): 512 |
| REG2_STEP_TIME | Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) 0 (64_CLOCKS): 64 1 (128_CLOCKS): 128 2 (256_CLOCKS): 256 3 (512_CLOCKS): 512 |
| VIDEO_DIV | Post-divider for video 0 (VIDEO_DIV_0): divide by 1 (Default) 1 (VIDEO_DIV_1): divide by 2 2 (VIDEO_DIV_2): divide by 1 3 (VIDEO_DIV_3): divide by 4 |